Posts Tagged ‘FBsim and the Fully Buffered DIMM Memory System Architecture’

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FBsim and the Fully Buffered DIMM Memory System Architecture

As DRAM device data rates increase in chase of ever increasing memory request rates, parallel bus limitations and cost constraints require a sharp decrease in load on the multi-drop buses between the devices and the memory controller, thus limiting the memory system’s scalability and failing to meet the capacity requirements of modern server and workstation applications. Full story
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